1. Field of the Invention
The present invention relates to a DRAM cell arrangement, and method for manufacturing same, having an increased packing density by constructing the selection transistor and the memory transistor of the self-amplifying memory cells as MOS transistors that are vertical in relation to a main surface of a substrate wherein the selection transistor and the memory transistor are arranged one over the other and are connected via a common source/drain region.
2. Description of the Prior Art
With increasing storage density per chip from one memory generation to the next, the surface of dynamic semiconductor memory cells has constantly been made smaller. For this purpose, beginning with the 4 Mbit memory generation, three-dimensional structures are required. Beginning with the 64 Mbit memory generation, the memory capacity has reached a value that can hardly be reduced any further, so that an approximately constant capacity has to be realized on a reduced cell surface. This leads to a considerable technological expense.
In contrast, in memory cells in which the signal charge is supplied not by a memory capacitor but rather by a supply voltage source, the level of the signal charge is not determined by the size of the memory capacity. In these memory cells, it is sufficient to store only a smaller charge in the storage capacitor which, when the memory cell is read out, activates a switching element in such a way that a conductive connection is produced between the supply voltage source and a bit line. Memory cells of this sort are designated self-amplifying memory cells, or gain memory cells.
A self-amplifying memory cell of this sort was, for example, proposed in M. Terauchi, A. Nitayama, F. Horiguchi and F. Masuoka, "A surrounding gate transistor (SGT) gain cell for ultra high density DRAMs," VLSI-Symp. Dig. Techn. Pap., p. 21, 1993. It includes an MOS transistor that surrounds a silicon column and, arranged thereunder, a junction field effect transistor. The MOS transistor works as a write transistor, while the junction field-effect transistor works as a readout transistor. For reading and writing information, two separate wordlines are required in this memory cell, so that two wordlines are provided for each memory cell.
In S. Shukuri, T. Kure, T. Kobayashi, Y. Gotoh and T. Nishida, "A semistatic complementary gain cell technology for sub-1 V supply DRAMs," IEEE Trans. Electron. Dev., vol. 41, p. 926, 1994, a self-amplifying memory cell was proposed that comprises a planar MOS transistor and a thin-film transistor that is complementary thereto and which is arranged in a trench. The planar MOS transistor serves for the writing of items of information and the thin-film transistor serves to read out items of information. The thin-film transistor includes a floating gate that is charged with a charge when items of information are written in. The gate electrodes of the two MOS transistors are connected with a wordline. They are driven with differing polarity, so that the production and switching of wordline voltages means an outlay in terms of circuitry.
From WO 92/01287, a self-amplifying dynamic MOS transistor memory cell is known that includes a selection transistor and a memory transistor. In this memory cell, the charge is stored in the gate/source capacitor of the memory transistor. The two transistors are connected in series, and include a common drain/source region. This common drain/source region is connected with the gate electrode of the memory transistor via a diode structure. During readout, the memory transistor is activated according to the stored information wherein it then closes a current path from a supply voltage to a bit line. In this cell type, selection and memory transistors are connected in series so that no specific line is required to read out the signal. The selection transistor and the memory transistor can thereby perform both as planar MOS transistors and as vertical MOS transistors, respectively arranged along the edge of a trench.